Analysis of Low Power Pulse Triggered Flip Flop

Flip Flops are critical timing elements in digital systems which has large impact on circuit speed and power consumption. The performance of flip flop is an important parameter to determine performance of whole synchronous circuit. In this paper, comparison of existing flip flops with different parameters is calculated. A new design a low power pulse triggered flip-flop (FF) has been proposed having a structure of explicit pulse triggered flip flop with a modified true phase single latch based on single feed through scheme. Pulse Triggered FF has a simple circuit which lowers the power consumption. The simulation is done on TANNER EDA using 90nm technology which verifies that Setup time, Hold time, D to Q delay, Average Power and optimal PDP has been reduced when compared with existing systems. P-FF gives a higher toggle rate for high-speed operations. The flip flop has shortened the delay, power etc which improves the speed, efficiency and power of the system.